1. FIELD OF THE INVENTION
This invention relates to a phase locked loop (hereinafter referred to as PLL) synthesizer.
2. DESCRIPTION OF THE PRIOR ART
FIG. 1 is a block diagram showing the construction of a PLL synthesizer as most commonly used.
In FIG. 1, 1 denotes a reference signal oscillator which employs usually a crystal vibrator and supplys a stable reference frequency f.sub.0. 2 denotes a phase detector which compares the phases of the signal with a frequency f.sub.0 from the signal oscillator 1 and an output with a frequency (f.sub.1 -f.sub.2)/N from a below-mentioned programmable counter and detects the phase difference. A d.c. voltage is generated corresponding to this phase difference. 3 denotes an integrator which integrates and smooths the output voltage of the phase detector 2. A continuous voltage component proportional to the phase difference is picked up and fed to the input terminal of a voltage controlled oscillator 4 of the next stage. The oscillation frequency f.sub.1 of the voltage controlled oscillator 4 is controlled to higher and lower values in proportion to an increase and a decrease of the controlled d.c. voltage applied to its input terminal respectively. 6 is a local oscillator. 7 is a mixer which mixes the output frequency f.sub.1 of the voltage controlled oscillator 4 and the output frequency f.sub.2 of the local oscillator 6 to obtain the frequencies f.sub., f.sub.1 + f.sub.2 and f.sub.1 - f.sub.2. In the prior art construction of this kind, a low pass filter 8 is employed in order to pass only the difference frequency f.sub.1 - f.sub.2 of the mixer signals 7 to the input terminal 51 - 20 of the programmable counter 51, which is operated with the input with the frequency f.sub.1 - f.sub.2. 5 denotes a programmable counter means consisting of a programmable counter 51 and a means for setting the frequency division ratio N. By switching the switch group 521-1, 521-2 . . . 521-n (n is an integer with n .gtoreq. 2) and supplying "0" or "1" digital input data to the input terminals 51-1, 51-2, 51-3, 51-4, . . . 51-n respectively, the counter means 5 can set the frequency division ratio to an arbitrary integer value within a certain range. If we assume that the figures of the input data terminals 51-1, 51-2, 51-3, 51-4, . . . 51-n increase in this order, the frequency division ratio N increases or decreases by 1 by switching the input data to the terminal 51-1 from "0" to "1" or from 1 to 0 respectively. The ratio N increases or decreases by 2 if the input data to the terminal 51-2 is changed from 0 to 1 or from 1 to 0 respectively. The ratio N increases or decreases by 4 if the input data to the terminal 51-3 is switched from 0 to 1 or from 1 to 0 respectively. It is so weighted that the ratio N increases or decreases by 2.sup.n-1 if the input data to the terminal 51-n is switched from 0 to 1. The output of the counter 51 having a frequency of (f.sub.1 - f.sub.2)/N is supplied to the phase detector. The system so operates as to cancel the phase difference and determine the output of the voltage controlled oscillator. Since the art is well known, detailed explanation of it will be omitted. For example, USP at. no. 3,845,394 may be referred to.
The prior art PLL synthesizer as shown in FIG. 1 has a defect that the difference frequency of the mixer 7 or the operating frequency of the programmable counter 51 can not be pulled up to the maximum operating frequency. In another word, it is difficult that the counter 51 operates at its maximum frequency. The reason is as follows. Although the programmable counter 51 is designed to be operable with an input having a maximum frequency of about 15 MHz, when such an input comes into the counter 51 by way of a conventional low pass filter 8, it is by-passed to the earth through stray capacitance. The amount of signal by-passed increases with frequency and causes a large attenuation of the input to the counter 51. No amplitude large enough to operate the counter 51 (at least IV) can be obtained. Hence, generally the maximum operating frequency of the counter is set at 10MHz for the TTL (transistor transistor logic). In a usual circuit construction, the operating frequency below which an amplitude enough to operate the counter 51 is obtained is set at 7 or 8 MHz.
Therefore, when the output frequency of the voltage controlled oscillator 4 increases, and hence the difference frequency f.sub.1 - f.sub.2 of the output of the mixer 7 or the operation frequency of the counter 51 increases above e.g. 10 MHz, the counter 51 stops its operation. In such a case, a complicated countermeasure should be necessary, i.e., either the oscillation frequency of the local oscillator 6 should be switched down so that the mixed difference between the frequencies of the voltage controlled oscillator 4 and the local oscillator 6 becomes less than 10 MHz, i.e., to about 7 or 8 MHz, or a frequency multiplier should be provided after the voltage controlled oscillator 4 so that the mixed difference frequency of the mixer 7 is so controlled as described above.